1. Field of the Invention
The present invention relates to static random access memory (SRAM) devices capable of performing burst operations, and more particularly, to SRAM memory devices capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single wordline, and which are capable of controlling data input/output for interruption of burst operation interruptions without having to employ complex control circuitry.
2. Description of the Related Art
In general, a burst operation is a rapid data access process that that automatically writes/reads a block of data to/from a series of consecutive addresses in response to an input of one external address. More specifically, when an external first (burst) address is applied to a memory device capable of performing a burst operation, the memory device will automatically determine a plurality of addresses that follow the first (burst) address without having to perform a decoding operation every cycle of a clock signal to select a plurality of memory cells respectively corresponding to the addresses following the first address. For example, assume a burst operation has a burst length of 8 bits. When an external first address is received and decoded by the memory device, seven addresses subsequent to the first address are automatically generated by the memory device internally, thus obviating the need to perform a decoding operation on eight addresses every cycle of the clock signal and allowing rapid data access of memory cells by performing a single address decoding operation.
FIG. 1 is a block diagram illustrating a conventional architecture of an SRAM device 100, which is capable of performing a burst operation. Referring to FIG. 1, the SRAM device 100 includes a memory block MBLK having a plurality of memory cells arranged in rows and columns. The memory cells in a given row are commonly connected by one of p wordlines (WL1˜WLp) which are selectively activated under operation of a row decoder 110. The memory block MBLK includes i column units (C0, C1 . . . Ci−1), where each column unit includes a column of memory cells commonly connected to a corresponding one of i bit line pairs including a bitline BL and complementary bitline /BL. Each column unit (C0˜Ci−1) includes a column decoder CD, which selectively activates a corresponding bitline pair BL and /BL.
The memory device 100 further comprises a peripheral circuit unit 120 connected to the memory block MBLK, which amplifies and outputs data that is read from the memory block MBLK, and which receives and writes data to be stored to the memory block MBLK. The memory block MBLK and the peripheral circuit unit 120 are connected to each other by a pair of data lines DL and /DL, wherein a data line DL is commonly coupled to the bit lines BL and wherein a complementary data line /DL is commonly coupled to the complementary bit lines /BL.
FIG. 2 is a block diagram illustrating a conventional architecture of the peripheral circuit unit 120 of FIG. 1. Referring to FIG. 2, the peripheral circuit unit 120 includes a sense amplification circuit S/A 121, which operates in response to a read control signal PSA, and a write driver W/D 122, which operates in response to a write control signal PWD. For the convenience of explanation, a data output buffer 210 and a data input buffer 220 are illustrated in FIG. 2 together with the peripheral circuit unit 120.
In general, with the conventional SRAM device 100 of FIG. 1 and peripheral circuit framework of FIG. 2, a read operation can be performed by selecting one of the p wordlines (WL1˜WLp) and one of the i bitline pairs BL, /BL to access data of a predetermined memory cell of the memory block MBLK. The data which is read from the selected memory cell is then transmitted via a pair of data lines DL and /DL to the peripheral circuit unit 120 and amplified by the sense amplification circuit S/A 121. Thereafter, the amplified data is transmitted to the data output buffer 210 and then output to an external input/output (I/O) terminal. On the other hand, with a write operation, data input to the external I/O terminal is first stored in the data input buffer 220, then transmitted to the write driver W/D 122, and then output to the data line pair DL, /DL to be written to predetermined memory cell that corresponds to a selected wordline and bit-line pair.
FIG. 3A is a timing diagram illustrating a conventional read burst operation that can be performed by the SRAM device 100 of FIG. 1, and FIG. 3B is a timing diagram illustrating a conventional write burst operation that can be performed by the SRAM device 100 of FIG. 1. Referring initially to FIG. 3A, assume that the burst length is 8 bits, i.e., an address designating a memory cell from which data is to be output is comprised of 8 bits. A burst operation can be performed by reading 8-bit data memory cells connected to a wordline WL corresponding to an address A0 as follows. To output a first data bit Q00, an external address AO is received and decoded to activate a corresponding wordline WL and a column decoder selection signal Y0 is applied to the column decoder in column unit CO to select a memory cell at column address A00. A read control signal PSA0 then activates the sense amplification circuit S/A 121 of FIG. 2 and data bit Q00 is output. To output a second data bit Q01, the wordline WL corresponding to address A0 is activated again and a column decoder selection signal Y1 is applied to the column decoder in column unit C1 to select a memory cell at column address A01. A read control signal PSA1 then activates the sense amplification circuit S/A 121 of FIG. 2 and data bit Q01 is output. This process is repeated again thereafter to sequentially output data bits Q02˜Q07, thus completing an 8-bit burst operation for address A0. With this process, the wordline for address A0 is repeatedly activated over column addresses A00˜A07 to output the 8-bit data Q00˜Q07.
Referring to FIG. 3B, assuming that the burst length is 8 bits, a burst operation can be performed by writing 8-bit data to memory cells connected to a wordline WL corresponding to an address A0 as follows. To store a first data bit D00, an external address A0 is received and decoded to activate a corresponding wordline WL and a column decoder selection signal Y0 is applied to the column decoder in column unit CO to select a memory cell at column address A00. A write control signal PWD0 then activates the write driver circuit W/D 122 of FIG. 2 and data bit D00 is stored as the memory cell selected by A0 and A00. To store a second data bit D01, the wordline WL corresponding to address A0 is activated again and a column decoder selection signal Y1 is applied to the column decoder in column unit C1 to select a memory cell. A write control signal PWD1 activates the write driver circuit W/D 122 of FIG. 2 and data bit D01 is output. This process is repeated again thereafter to sequentially store data bits D02˜D07, thus completing an 8-bit burst operation for address A0. With this process, the wordline for address A0 is repeatedly activated to store the 8-bit data D00˜D07.
As described above, with the conventional SRAM device 100, a data access operation is performed by activating one of the p wordlines (WL1˜WLp) and one of the i bitline pairs BL and /BL to select one memory cell and read/write one data bit. In this regard, although the SRAM circuitry for writing/reading data to/from each of the memory cells in the memory block MBLK is relatively simple, the SRAM device 100 consumes a considerable amount of current when having to activate a wordlines WL to perform a data access operation for one memory cell (i.e., one data bit). Indeed, in the conventional burst operations of FIGS. 3A and 3B, the SRAM device 100 drives almost all of its circuit units, including the memory block MBLK and the peripheral circuit unit 120, every cycle of a clock signal, which increases power consumption and reduces operating speed of the SRAM device 100.